1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for generating timing signals for operating a fast on-chip cache.
2. History of the Prior Art
In computer systems, the access of main memory to retrieve information often takes a substantial portion of the operational time. This occurs for various reasons. First, main memory is made of random access memory. Such memory is often sufficiently large that the cost is kept within bounds by using relatively slow memory. Second, main memory is typically accessed over a system bus which provides a less than optimum interface between the main memory and the central processing unit of the system.
For this reason, the use of cache memories to increase system speed has become prevalent in more advanced systems. A cache memory makes use of a relatively small amount of fast random access memory in which recently used instructions and data are stored as they are used by a processor. Such instructions and data are then available in the cache to be more rapidly accessed by the associated processor when next required. The basic theory of caching is that, in general, information which has been recently used is more likely to be used sooner than is other information. The cache memory is often both physically faster than the random access memory used for main memory and is arranged so that it may be addressed more rapidly than may main memory.
One way to increase the speed of cache memory for very fast computers is to place that cache memory on the same chip as the processor it serves. This eliminates delays caused by interfacing off-chip transfers and allows the circuitry to be optimized for use with the particular processor. However, in attempting to provide cache memory for very fast processors which are expected to process one instruction during each clock cycle of operation, the need for accurate timing of the signals controlling cache memory operation becomes dominant. In very fast caches, a limiting factor becomes the number of operations which must be accomplished within a clock cycle of operation. In some cases the time required to accomplish certain of these operations is longer than the time allotted by the system clock. While the problem may be solved by lengthening the clock period or by taking more than one clock period to accomplish certain cache operations, this is undesirable.